The present invention is related to electronic circuits, and more specifically to voltage restriction circuits for use with LVDS input buffers.
Differential signaling has been in existence for many years. For example, teletypes were some of the first.equipment to use differential signaling to communicate. Electronic devices (i.e. computers) often communicate between ports by means of Low Voltage Differential Signaling (LVDS) driver and receiver pairs.
LVDS is a differential signaling technique commonly used in data transmission systems. A low voltage differential signal produced by a line driver typically has peak-to-peak amplitudes in the range from 250 mV to 450 mV. The low voltage swing minimizes power dissipation, while maintaining high transmission speeds. Typical transmission speeds are over 100 Mbps (Mega-bits per second).
LVDS input buffers are designed to receive a wide variety of input signals while producing a fairly constant output signal. The input signals received by the LVDS input buffers may vary in frequency, peak-to-peak voltage, as well as common-mode voltage. Some LVDS input buffers, however, generate jitter that may cause problems within the LVDS system.
The present invention is directed at restricting the differential output voltage (VOD) for LVDS input buffers. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit.
According to one aspect of the invention, the VOD of the LVDS input buffer is restricted when a predetermined threshold has been reached. According to one embodiment of the invention, the predetermined threshold is about 650 mV.
According to another aspect of the invention, clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage to be below or at the predetermined threshold. The clamping circuits are activated in response to the VOD reaching the predetermined threshold.
According to yet another aspect of the invention, an alternate signal path is created when a clamping circuit is activated. The alternate current path helps to ensure that the output signals from the VOD restriction circuit are maintained at the previous levels before the clamping circuits activate.
According to another aspect of the invention, an apparatus for restricting a differential output voltage of an input buffer is provided. The apparatus includes a first and second current-limiting device for producing the differential output voltage. The apparatus also includes a first and second clamping circuit that restricts the VOD based upon a predetermined threshold.
According to a further aspect of the invention, a method for restricting a differential output voltage of an LVDS input buffer is provided. The differential output voltage is restricted to help ensure that the VOD does not exceed a predetermined threshold. The VOD is monitored to determine when the VOD reaches the predetermined threshold. Clamping is activated when the predetermined threshold is reached thereby restricting VOD. An alternate current path is also provided allowing the output signal to be maintained during the clamping. The clamping is deactivated when the measured VOD is less than the predetermined threshold.